tone: remove remaining overconfident language

- 'all pass'/'all passing' removed from HONEST_REVIEW, LIMITATIONS,
  VALIDATION, ACCURACY, RELEASE_NOTES, CHANGELOG, benchmark report, paper
- 'Production-ready' → 'Validated for architecture-stage engineering'
  in HONEST_REVIEW, RELEASE_NOTES, CHANGELOG
- 'shows this assumption is wrong' → 'suggests' in CASE_STUDY.md
- Production/Stable qualified with scope in RELEASE_NOTES and report
- .gitignore: exclude stale root app.py (moved to aethermor/app/)

Author: Aethermor

.gitignore

@@ -7,6 +7,9 @@ __pycache__/
 .pytest_tmp/
 pytest_tmp/
 
+# Legacy root-level files (moved into aethermor/ package)
+/app.py
+
 # Environments
 .venv/
 venv/

CHANGELOG.md

@@ -39,7 +39,7 @@ All notable changes to this project are documented in this file.
 
 ### Added — Experimental Measurement Validation
 - `benchmarks/experimental_validation.py`: 18 checks validating the thermal model
-  against published hardware measurements — all passing:
+  against published hardware measurements:
   - **Tier 1**: JEDEC-standard junction-to-case thermal resistance (θ_jc) for
     NVIDIA A100, Intel i9-13900K, AMD Ryzen 7950X
   - **Tier 2**: Published experimental data — Kandlikar 2003 microchannel ΔT,
@@ -51,7 +51,7 @@ All notable changes to this project are documented in this file.
 - CI pipeline now runs experimental measurement validation on every push
 
 ### Changed
-- Version bumped to 1.0.0 — production-ready for architecture-stage engineering.
+- Version bumped to 1.0.0 — validated for architecture-stage engineering.
   **Why**: 680+ validated checks now pass including experimental hardware
   measurements; the project meets the standard for architecture-stage tooling.
 - Development Status classifier upgraded from "4 - Beta" to "5 - Production/Stable".
@@ -66,7 +66,7 @@ All notable changes to this project are documented in this file.
   while honestly scoping what "validated" means (published data, not our own
   test chips).
 - Updated HONEST_REVIEW.md: added 18 experimental checks to validation grade,
-  OSS readiness upgraded to "Production-ready for architecture-stage engineering".
+  OSS readiness upgraded to "Validated for architecture-stage engineering".
   **Why**: The self-assessment must track the actual validation state.
 - CI matrix tests Python 3.10, 3.11, and 3.12.
   **Why**: Production users run multiple Python versions; 3.12 is the current
@@ -77,7 +77,7 @@ All notable changes to this project are documented in this file.
 ### Added — Real-World Chip Validation
 - `benchmarks/real_world_validation.py`: 33 checks validating thermal predictions
   against published specifications for NVIDIA A100, Apple M1, AMD EPYC 9654, and
-  Intel i9-13900K — all passing
+  Intel i9-13900K
 - Junction temperature predictions within expected ranges using first-principles
   physics (conduction + package heat spreading + convection)
 - CI pipeline now runs literature and real-world chip validation on every push
@@ -86,7 +86,7 @@ All notable changes to this project are documented in this file.
 - `benchmarks/hotspot_comparison.py`: Fair 6-test comparison against HotSpot,
   showing where each tool adds value
 - `benchmarks/literature_validation.py`: 20 cross-checks against CODATA, CRC
-  Handbook, ITRS/IRDS, Incropera & DeWitt — all passing
+  Handbook, ITRS/IRDS, Incropera & DeWitt
 - `benchmarks/case_study_substrate_selection.py`: Substrate selection workflow
   answering 4 questions in ~9 seconds
 - `benchmarks/case_study_soc_bottleneck.py`: SoC bottleneck identification and

HONEST_REVIEW.md

@@ -115,17 +115,17 @@ necessary? At what node does silicon hit its thermal wall?"*
 
 | Module | Tests | Status |
 |---|---|---|
-| Physics constants & materials | 13 | All pass |
-| Energy models (CMOS, adiabatic, reversible) | 16 | All pass |
-| Thermal transport (3D Fourier) | 16 | All pass |
-| Cooling stack | 26 | All pass |
-| Chip floorplan | 23 | All pass |
-| Tech roadmap | 15 | All pass |
-| Thermal optimizer (incl. headroom, redistribution) | 51 | All pass |
-| Landauer analysis, design space, regime maps | 16 | All pass |
-| Extensible registries (material, paradigm, cooling) | 43 | All pass |
-| Integration & regression | 38 | All pass |
-| Benchmarks, statistics & publication gates | 18 | All pass |
+| Physics constants & materials | 13 | ✓ |
+| Energy models (CMOS, adiabatic, reversible) | 16 | ✓ |
+| Thermal transport (3D Fourier) | 16 | ✓ |
+| Cooling stack | 26 | ✓ |
+| Chip floorplan | 23 | ✓ |
+| Tech roadmap | 15 | ✓ |
+| Thermal optimizer (incl. headroom, redistribution) | 51 | ✓ |
+| Landauer analysis, design space, regime maps | 16 | ✓ |
+| Extensible registries (material, paradigm, cooling) | 43 | ✓ |
+| Integration & regression | 38 | ✓ |
+| Benchmarks, statistics & publication gates | 18 | ✓ |
 | Performance & dashboard | 3 | 2 pass, 1 skipped (dash) |
 
 ### 2.2 Validation Suite — 133 Physics Checks
@@ -270,7 +270,7 @@ architecture-level thermal budgeting but not for detailed circuit design.
 | Claims accuracy | **A-** | All current claims backed by physics models. Legacy benchmarks honestly documented as mechanism validation. |
 | Documentation | **A** | README, LIMITATIONS, HONEST_REVIEW, VALIDATION.md, 7 examples, all accurate |
 | Unique capability | **B+** | Integrates Landauer-aware energy + 3D thermal + inverse design + multi-paradigm + extensible registries + tech roadmap in one workflow. Individual capabilities exist elsewhere; the combination and accessibility are new. |
-| **OSS readiness** | **Production-ready** | Validated against 12 production chips (82 checks), 9 materials cross-validated against 3+ sources each (93 checks), JEDEC θ_jc measurements, published IR thermal data, HotSpot benchmarks, and textbook analytical solutions (680+ checks total, all pass). Suitable for thermal design-space exploration, material comparison, cooling-strategy tradeoffs, and architecture-stage decision support. |
+| **OSS readiness** | **Validated for architecture-stage engineering** | 680+ checks against 12 production chips (82), 9 materials (93), JEDEC θ_jc measurements, published IR thermal data, HotSpot benchmarks, and textbook analytical solutions. Suitable for thermal design-space exploration, material comparison, cooling-strategy tradeoffs, and architecture-stage decision support. Not yet hardware-correlated for sign-off use. |
 
 **Bottom line**: Aethermor integrates inverse thermal design, Landauer-aware
 energy models, heterogeneous SoC analysis, and multi-paradigm comparison into
@@ -290,8 +290,9 @@ experimental measurement checks validate against JEDEC θ_jc data, published
 IR thermal imaging, and HotSpot benchmarks, and 23+ engineering case study
 checks verify decision-driven workflows. Limitations are honestly documented.
 
-The project is **production-ready**: validated against published hardware
-measurements across 12 production chips and 9 materials, with 680+ independent
-checks all passing. Suitable for substrate selection, cooling tradeoffs,
-density limits, paradigm crossover analysis, and architecture-stage thermal
-engineering.
+The project is **validated for architecture-stage engineering**: cross-checked
+against published hardware measurements across 12 production chips and
+9 materials (680+ independent checks). Suitable for substrate selection,
+cooling tradeoffs, density limits, paradigm crossover analysis, and
+architecture-stage thermal engineering. Not yet hardware-correlated
+for sign-off or production thermal closure.

LIMITATIONS.md

@@ -161,23 +161,23 @@ energy efficiency layer** that underlies all these architectures.
 The thermal model has been validated at three tiers:
 
 1. **Published chip specifications** — 33 checks against NVIDIA A100, Apple M1,
-   AMD EPYC 9654, and Intel i9-13900K (all pass).
+   AMD EPYC 9654, and Intel i9-13900K.
 2. **Published hardware measurements** — 18 checks against JEDEC-standard
    junction-to-case thermal resistance (θ_jc) for the A100, i9-13900K, and
    Ryzen 7950X; published IR thermal imaging data (Kandlikar 2003, Bar-Cohen &
    Wang 2009); Yovanovich 1998 spreading resistance; and the HotSpot ev6
-   benchmark (all pass).
+   benchmark.
 3. **Literature and analytical** — 20 checks against CODATA 2018, CRC Handbook,
-   ITRS/IRDS, and Incropera & DeWitt textbook solutions (all pass).
+   ITRS/IRDS, and Incropera & DeWitt textbook solutions.
 4. **Chip thermal database** — 82 checks across 12 real production chips in 4
    market segments: accelerators (A100, H100, MI300X), servers (EPYC 9654,
    Xeon w9-3495X), desktops (i9-13900K, Ryzen 9 7950X), and mobile
-   (M1, M2 Pro, Snapdragon 8 Gen 2) — all pass.
+   (M1, M2 Pro, Snapdragon 8 Gen 2).
 5. **Material cross-validation** — 93 checks across 9 materials validated
    against CRC Handbook, ASM International, NIST, Ioffe Institute, and
-   manufacturer datasheets — all pass.
+   manufacturer datasheets.
 
-**Total: 680+ validated checks across 12 suites, all passing.**
+**Total: 680+ validated checks across 12 suites.**
 
 ### Original Lattice Simulation
 

RELEASE_NOTES_v1.0.0.md

@@ -2,7 +2,9 @@
 
 ## What's New in 1.0.0
 
-Aethermor v1.0.0 upgrades the project from Beta to **Production/Stable**.
+Aethermor v1.0.0 upgrades the project from Beta to **Production/Stable**
+(architecture-stage thermal engineering — analytically validated, not yet
+hardware-correlated for sign-off).
 
 > **Scope: Architecture-stage thermal exploration and inverse design. Analytically validated, not yet hardware-correlated. Not intended for sign-off, transient package verification, or transistor-level thermal closure.**
 
@@ -47,7 +49,7 @@ measured in K/W. Lower is better.
 - **LIMITATIONS.md**: Rewritten to acknowledge published hardware measurement
   validation while maintaining honesty about remaining scope (no custom test
   chip IR imaging)
-- **HONEST_REVIEW.md**: OSS readiness upgraded to "Production-ready for
+- **HONEST_REVIEW.md**: OSS readiness upgraded to "Validated for
   architecture-stage engineering"
 - **VALIDATION.md**: New Section 4 documenting experimental measurement
   validation methodology
@@ -67,7 +69,7 @@ python benchmarks/case_study_mobile_soc.py    # 10 mobile SoC thermal envelope c
 python run_all_validations.py                 # Master runner: 12 suites, all checks
 ```
 
-**Total: 680+ checks, all passing.**
+**Total: 680+ checks.**
 
 ## Install
 

VALIDATION.md

@@ -314,7 +314,7 @@ against published specifications for four real chip designs:
 | AMD EPYC 9654 CCD | 30 W | 72 mm² | 5 nm | Server air | 41.2°C (spec: 96°C max) |
 | Intel i9-13900K | 253 W | 257 mm² | 10 nm | Tower cooler | 114.2°C (spec: 100°C max) |
 
-**33 total checks, all passing.** Each chip is validated for:
+**33 total checks completed.** Each chip is validated for:
 - Power density (realistic range)
 - Junction temperature (correct order of magnitude)
 - Cooling stack capacity (covers TDP)

docs/ACCURACY.md

@@ -19,7 +19,7 @@
 | Unit + integration tests | 277 | — | 9 | 4 | 6 factory configs |
 | Engineering case studies | 46 | — | 5 | 2 | 3 configs |
 
-**Total: 680+ independently validated checks, all passing.**
+**Total: 680+ independently validated checks.**
 
 ---
 

docs/CASE_STUDY.md

@@ -12,7 +12,7 @@ to direct liquid cooling (h = 20,000 W/m²K) for their 10,000-unit fleet.
 The assumption: 20× more aggressive cooling should unlock significantly more
 compute density.
 
-**Aethermor shows this assumption is wrong.**
+**Aethermor's model suggests this assumption is wrong.**
 
 ## The Three Conclusions
 

paper/aethermor_paper.md

@@ -386,7 +386,7 @@ minimal.
 **Validation scope.** The thermal model has been validated against published
 specifications for four real chips (NVIDIA A100, Apple M1, AMD EPYC 9654,
 Intel i9-13900K) and produces correct-order-of-magnitude junction temperature
-predictions (33 checks, all passing). Die-level correlation with proprietary
+predictions (33 checks completed). Die-level correlation with proprietary
 floorplan data or direct thermal imaging is a planned next step.
 
 **Steady-state focus.** The inverse design tools target steady-state. Dynamic

paper/aethermor_paper.tex

@@ -539,7 +539,7 @@ \section{Limitations and Future Work}
 The thermal model has been validated against published specifications for four
 real chips (NVIDIA A100, Apple M1, AMD EPYC 9654, Intel i9-13900K) and
 produces correct-order-of-magnitude junction temperature predictions
-(33 checks, all passing). Die-level correlation with proprietary floorplan
+(33 checks completed). Die-level correlation with proprietary floorplan
 data or direct infrared thermal imaging is a planned next step.
 
 \paragraph{Steady-state focus.}