Adjust USB connector hole size to match FAB requirements

Author: Tyler-Ward

stack-light.kicad_pcb

@@ -58,7 +58,7 @@
     (mod_text_size 1 1)
     (mod_text_width 0.15)
     (pad_size 0.69 0.69)
-    (pad_drill 0.4)
+    (pad_drill 0.35)
     (pad_to_mask_clearance 0)
     (aux_axis_origin 0 0)
     (visible_elements 7FFFFFFF)
@@ -1503,9 +1503,9 @@
     (fp_text user %R (at 0 0) (layer F.Fab)
       (effects (font (size 0.8 0.8) (thickness 0.12)))
     )
-    (pad 2 smd roundrect (at 1.4625 0) (size 1.125 2.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.222222)
+    (pad 2 smd roundrect (at 1.4625 0) (size 1.125 2.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2222213333333333)
       (net 6 GND))
-    (pad 1 smd roundrect (at -1.4625 0) (size 1.125 2.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.222222)
+    (pad 1 smd roundrect (at -1.4625 0) (size 1.125 2.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2222213333333333)
       (net 9 +12V))
     (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_1210_3225Metric.wrl
       (at (xyz 0 0 0))
@@ -1539,9 +1539,9 @@
     (fp_text user %R (at 0 0) (layer F.Fab)
       (effects (font (size 0.8 0.8) (thickness 0.12)))
     )
-    (pad 2 smd roundrect (at 1.4625 0) (size 1.125 2.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.222222)
+    (pad 2 smd roundrect (at 1.4625 0) (size 1.125 2.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2222213333333333)
       (net 6 GND))
-    (pad 1 smd roundrect (at -1.4625 0) (size 1.125 2.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.222222)
+    (pad 1 smd roundrect (at -1.4625 0) (size 1.125 2.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2222213333333333)
       (net 9 +12V))
     (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_1210_3225Metric.wrl
       (at (xyz 0 0 0))
@@ -2702,9 +2702,9 @@
     (fp_text user %R (at 0 0) (layer B.Fab)
       (effects (font (size 0.5 0.5) (thickness 0.08)) (justify mirror))
     )
-    (pad 2 smd roundrect (at 0.9125 0) (size 1.025 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.2439014634146341)
+    (pad 2 smd roundrect (at 0.9125 0) (size 1.025 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.2439004878048781)
       (net 9 +12V))
-    (pad 1 smd roundrect (at -0.9125 0) (size 1.025 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.2439014634146341)
+    (pad 1 smd roundrect (at -0.9125 0) (size 1.025 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.2439004878048781)
       (net 7 "Net-(C7-Pad2)"))
     (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0805_2012Metric.wrl
       (at (xyz 0 0 0))
@@ -2738,9 +2738,9 @@
     (fp_text user %R (at 0 0 90) (layer F.Fab)
       (effects (font (size 0.8 0.8) (thickness 0.12)))
     )
-    (pad 2 smd roundrect (at 1.4625 0 90) (size 1.125 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2222213333333333)
+    (pad 2 smd roundrect (at 1.4625 0 90) (size 1.125 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2222204444444444)
       (net 2 POE_VIN))
-    (pad 1 smd roundrect (at -1.4625 0 90) (size 1.125 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2222213333333333)
+    (pad 1 smd roundrect (at -1.4625 0 90) (size 1.125 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2222204444444444)
       (net 5 "Net-(C5-Pad2)"))
     (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_1206_3216Metric.wrl
       (at (xyz 0 0 0))
@@ -4390,7 +4390,7 @@
     )
   )
 
-  (module Connector_USB:USB_C_Receptacle_GCT_USB4085 (layer F.Cu) (tedit 603BA80E) (tstamp 600D365D)
+  (module Connector_USB:USB_C_Receptacle_GCT_USB4085 (layer F.Cu) (tedit 61217F33) (tstamp 600D365D)
     (at 106.65 96 270)
     (descr "USB 2.0 Type C Receptacle, https://gct.co/Files/Drawings/USB4085.pdf")
     (tags "USB Type-C Receptacle Through-hole Right angle")
@@ -4430,37 +4430,37 @@
       (net 6 GND))
     (pad S1 thru_hole oval (at -1.35 0.98 270) (size 0.9 2.4) (drill oval 0.6 2.1) (layers *.Cu *.Mask)
       (net 6 GND))
-    (pad B6 thru_hole circle (at 3.4 1.35 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad B6 thru_hole circle (at 3.4 1.35 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 65 "Net-(J4-PadA6)"))
-    (pad B1 thru_hole circle (at 5.95 1.35 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad B1 thru_hole circle (at 5.95 1.35 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 6 GND))
-    (pad B4 thru_hole circle (at 5.1 1.35 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad B4 thru_hole circle (at 5.1 1.35 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 51 /Processor/USB_VBUS))
-    (pad B5 thru_hole circle (at 4.25 1.35 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad B5 thru_hole circle (at 4.25 1.35 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 32 "Net-(J4-PadB5)"))
-    (pad B12 thru_hole circle (at 0 1.35 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad B12 thru_hole circle (at 0 1.35 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 6 GND))
-    (pad B8 thru_hole circle (at 1.7 1.35 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad B8 thru_hole circle (at 1.7 1.35 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 31 "Net-(J4-PadB8)"))
-    (pad B7 thru_hole circle (at 2.55 1.35 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad B7 thru_hole circle (at 2.55 1.35 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 66 "Net-(J4-PadA7)"))
-    (pad B9 thru_hole circle (at 0.85 1.35 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad B9 thru_hole circle (at 0.85 1.35 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 51 /Processor/USB_VBUS))
-    (pad A12 thru_hole circle (at 5.95 0 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad A12 thru_hole circle (at 5.95 0 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 6 GND))
-    (pad A9 thru_hole circle (at 5.1 0 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad A9 thru_hole circle (at 5.1 0 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 51 /Processor/USB_VBUS))
-    (pad A8 thru_hole circle (at 4.25 0 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad A8 thru_hole circle (at 4.25 0 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 33 "Net-(J4-PadA8)"))
-    (pad A7 thru_hole circle (at 3.4 0 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad A7 thru_hole circle (at 3.4 0 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 66 "Net-(J4-PadA7)"))
-    (pad A6 thru_hole circle (at 2.55 0 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad A6 thru_hole circle (at 2.55 0 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 65 "Net-(J4-PadA6)"))
-    (pad A5 thru_hole circle (at 1.7 0 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad A5 thru_hole circle (at 1.7 0 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 34 "Net-(J4-PadA5)"))
-    (pad A4 thru_hole circle (at 0.85 0 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad A4 thru_hole circle (at 0.85 0 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 51 /Processor/USB_VBUS))
-    (pad A1 thru_hole circle (at 0 0 270) (size 0.69 0.69) (drill 0.4) (layers *.Cu *.Mask)
+    (pad A1 thru_hole circle (at 0 0 270) (size 0.69 0.69) (drill 0.35) (layers *.Cu *.Mask)
       (net 6 GND))
     (model ${KISYS3DMOD}/Connector_USB.3dshapes/USB_C_Receptacle_GCT_USB4085.wrl
       (at (xyz 0 0 0))
@@ -7376,7 +7376,7 @@
   (segment (start 135 86) (end 134.5 85.5) (width 0.25) (layer F.Cu) (net 129))
   (segment (start 139.75 86) (end 135 86) (width 0.25) (layer F.Cu) (net 129))
 
-  (zone (net 2) (net_name POE_VIN) (layer F.Cu) (tstamp 61222746) (hatch edge 0.508)
+  (zone (net 2) (net_name POE_VIN) (layer F.Cu) (tstamp 6122288D) (hatch edge 0.508)
     (priority 2)
     (connect_pads yes (clearance 0.2))
     (min_thickness 0.254)
@@ -7400,7 +7400,7 @@
       )
     )
   )
-  (zone (net 15) (net_name "Net-(D4-Pad2)") (layer F.Cu) (tstamp 61222743) (hatch edge 0.508)
+  (zone (net 15) (net_name "Net-(D4-Pad2)") (layer F.Cu) (tstamp 6122288A) (hatch edge 0.508)
     (priority 2)
     (connect_pads yes (clearance 0.2))
     (min_thickness 0.254)
@@ -7420,7 +7420,7 @@
       )
     )
   )
-  (zone (net 3) (net_name GNDPWR) (layer F.Cu) (tstamp 61222740) (hatch edge 0.508)
+  (zone (net 3) (net_name GNDPWR) (layer F.Cu) (tstamp 61222887) (hatch edge 0.508)
     (priority 2)
     (connect_pads yes (clearance 0.2))
     (min_thickness 0.254)
@@ -7484,7 +7484,7 @@
       )
     )
   )
-  (zone (net 1) (net_name POE_VSS) (layer F.Cu) (tstamp 6122273D) (hatch edge 0.508)
+  (zone (net 1) (net_name POE_VSS) (layer F.Cu) (tstamp 61222884) (hatch edge 0.508)
     (priority 2)
     (connect_pads yes (clearance 0.2))
     (min_thickness 0.254)
@@ -7502,7 +7502,7 @@
       )
     )
   )
-  (zone (net 2) (net_name POE_VIN) (layer F.Cu) (tstamp 6122273A) (hatch edge 0.508)
+  (zone (net 2) (net_name POE_VIN) (layer F.Cu) (tstamp 61222881) (hatch edge 0.508)
     (priority 2)
     (connect_pads yes (clearance 0.2))
     (min_thickness 0.254)
@@ -7521,7 +7521,7 @@
       )
     )
   )
-  (zone (net 5) (net_name "Net-(C5-Pad2)") (layer F.Cu) (tstamp 61222737) (hatch edge 0.508)
+  (zone (net 5) (net_name "Net-(C5-Pad2)") (layer F.Cu) (tstamp 6122287E) (hatch edge 0.508)
     (priority 2)
     (connect_pads yes (clearance 0.2))
     (min_thickness 0.254)
@@ -7539,7 +7539,7 @@
       )
     )
   )
-  (zone (net 6) (net_name GND) (layer F.Cu) (tstamp 61222734) (hatch edge 0.508)
+  (zone (net 6) (net_name GND) (layer F.Cu) (tstamp 6122287B) (hatch edge 0.508)
     (connect_pads (clearance 0.2))
     (min_thickness 0.254)
     (fill yes (arc_segments 32) (thermal_gap 0.3) (thermal_bridge_width 0.508))
@@ -9270,7 +9270,7 @@
       )
     )
   )
-  (zone (net 6) (net_name GND) (layer B.Cu) (tstamp 61222731) (hatch edge 0.508)
+  (zone (net 6) (net_name GND) (layer B.Cu) (tstamp 61222878) (hatch edge 0.508)
     (connect_pads (clearance 0.2))
     (min_thickness 0.254)
     (fill yes (arc_segments 32) (thermal_gap 0.3) (thermal_bridge_width 0.508))
@@ -10710,7 +10710,7 @@
       )
     )
   )
-  (zone (net 2) (net_name POE_VIN) (layer B.Cu) (tstamp 6122272E) (hatch edge 0.508)
+  (zone (net 2) (net_name POE_VIN) (layer B.Cu) (tstamp 61222875) (hatch edge 0.508)
     (priority 2)
     (connect_pads yes (clearance 0.2))
     (min_thickness 0.254)
@@ -10747,7 +10747,7 @@
       )
     )
   )
-  (zone (net 3) (net_name GNDPWR) (layer B.Cu) (tstamp 6122272B) (hatch edge 0.508)
+  (zone (net 3) (net_name GNDPWR) (layer B.Cu) (tstamp 61222872) (hatch edge 0.508)
     (priority 1)
     (connect_pads yes (clearance 0.4))
     (min_thickness 0.254)
@@ -10821,7 +10821,7 @@
       )
     )
   )
-  (zone (net 3) (net_name GNDPWR) (layer F.Cu) (tstamp 61222728) (hatch edge 0.508)
+  (zone (net 3) (net_name GNDPWR) (layer F.Cu) (tstamp 6122286F) (hatch edge 0.508)
     (priority 1)
     (connect_pads yes (clearance 0.4))
     (min_thickness 0.254)
@@ -10864,7 +10864,7 @@
       )
     )
   )
-  (zone (net 1) (net_name POE_VSS) (layer F.Cu) (tstamp 61222725) (hatch edge 0.508)
+  (zone (net 1) (net_name POE_VSS) (layer F.Cu) (tstamp 6122286C) (hatch edge 0.508)
     (priority 2)
     (connect_pads yes (clearance 0.4))
     (min_thickness 0.254)
@@ -10894,7 +10894,7 @@
       )
     )
   )
-  (zone (net 1) (net_name POE_VSS) (layer B.Cu) (tstamp 61222722) (hatch edge 0.508)
+  (zone (net 1) (net_name POE_VSS) (layer B.Cu) (tstamp 61222869) (hatch edge 0.508)
     (priority 3)
     (connect_pads yes (clearance 0.4))
     (min_thickness 0.254)
@@ -10915,7 +10915,7 @@
       )
     )
   )
-  (zone (net 8) (net_name "Net-(C7-Pad1)") (layer F.Cu) (tstamp 6122271F) (hatch edge 0.508)
+  (zone (net 8) (net_name "Net-(C7-Pad1)") (layer F.Cu) (tstamp 61222866) (hatch edge 0.508)
     (priority 2)
     (connect_pads yes (clearance 0.2))
     (min_thickness 0.254)