3636CdlNetlistWriter::CdlNetlistWriter (
3737 QTextStream& netlistStream,
3838 Schematic* schematic,
39- bool resolveSpicePrefix) :
39+ bool resolveSpicePrefix,
40+ const QString& subCircuitName) :
4041 a_netlistStream(netlistStream),
4142 a_schematic(schematic),
4243 a_resolveSpicePrefix(resolveSpicePrefix),
4344 a_netListString(),
4445 a_netListStringStream(&a_netListString, QIODeviceBase::WriteOnly),
45- a_effectiveNetlistStream(resolveSpicePrefix ? a_netListStringStream : a_netlistStream)
46+ a_effectiveNetlistStream(resolveSpicePrefix ? a_netListStringStream : a_netlistStream),
47+ a_pinInfo(),
48+ a_subCircuitName(subCircuitName)
4649{
4750 if (a_resolveSpicePrefix)
4851 {
@@ -66,7 +69,7 @@ bool CdlNetlistWriter::write()
6669
6770 startNetlist ();
6871
69- a_effectiveNetlistStream << " .END\n " ;
72+ a_effectiveNetlistStream << " .ENDS \n " << " . END\n " ;
7073
7174 if (a_resolveSpicePrefix)
7275 {
@@ -76,6 +79,8 @@ bool CdlNetlistWriter::write()
7679 a_netlistStream << a_netListString;
7780 }
7881
82+ a_schematic->resetNetNameMapping ();
83+
7984 return true ;
8085}
8186
@@ -163,6 +168,8 @@ int CdlNetlistWriter::prepareNetlist()
163168 return -10 ;
164169 }
165170
171+ a_schematic->setNetNameMapping (a_pinInfo);
172+
166173 return numPorts;
167174}
168175
@@ -171,7 +178,7 @@ void CdlNetlistWriter::startNetlist()
171178 QString s;
172179
173180 // Parameters, Initial conditions, Options
174- for (Component *pc : a_schematic->a_DocComps )
181+ for (Component *pc: a_schematic->a_DocComps )
175182 {
176183 if (pc->isEquation )
177184 {
@@ -180,17 +187,37 @@ void CdlNetlistWriter::startNetlist()
180187 }
181188 }
182189
190+ // always wrap the main netlist in a subcircuit
191+ a_effectiveNetlistStream << " .SUBCKT " << a_subCircuitName;
192+ for (auto pinInfo: a_pinInfo)
193+ {
194+ a_effectiveNetlistStream << " " << pinInfo.first ;
195+ }
196+ a_effectiveNetlistStream << " \n " ;
197+
183198 // global net 0 is always ground
184- a_effectiveNetlistStream << " .GLOBAL 0:G\n " ;
199+ a_effectiveNetlistStream << " *.GLOBAL 0:G\n " ;
200+
201+ if (!a_pinInfo.isEmpty ())
202+ {
203+ a_effectiveNetlistStream << " *.PININFO" ;
204+
205+ for (auto pinInfo: a_pinInfo)
206+ {
207+ a_effectiveNetlistStream << " " << pinInfo.first << " :" << pinInfo.second ;
208+ }
209+
210+ a_effectiveNetlistStream << " \n " ;
211+ }
185212
186213 // Components
187- for (Component *pc : a_schematic->a_DocComps )
214+ for (Component *pc: a_schematic->a_DocComps )
188215 {
189216 if (a_schematic->getIsAnalog () && !pc->isSimulation && !pc->isEquation )
190217 {
191218 s = pc->getSpiceNetlist (spicecompat::CDL);
192219
193- a_effectiveNetlistStream << s ;
220+ a_effectiveNetlistStream << (s == " \n " ? " " : s) ;
194221 }
195222 }
196223
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