`VerilogWriter::writeAssigns()` omitted `assign` statement when a feed-through net name matches output port name

[jhkim-pii]

VerilogWriter::writeAssigns(const Instance *inst) assumes that a feed-through net name should match its input port name.

• If a feed-through net name matches its input port name, assign statement is correctly generated when write_verilog command is exectued because the net name is different to its output port name.

Case 1.
(input term name:  IN)  -->  (feed-through wire name: IN)  --> (output term name: OUT)

[ Verilog output by write_verilog command ]

module sub (IN, OUT);
  input IN;
  output OUT;
  assign OUT = IN;             // Correct
endmodule

• But if a feed-through net name matches its output port name, assign statement is not generated.

Case 2.
(input term name:  IN)  -->  (feed-through wire name: OUT)  --> (output term name: OUT)

[ Verilog output by write_verilog command ]

module sub (IN, OUT);
  input IN;
  output OUT;
                         // ERROR. assign statement is missing
endmodule

It would be nice if VerilogWriter::writeAssigns() can generate the assign statement correctly even if the feed-through net name is the same as the output term name.

[dsengupta0628]

If I wanted to reproduce the issue, what Verilog should I be reading with or without the explicit assignment?
i.e.,

module sub (IN, OUT);
  input IN;
  output OUT;
endmodule

OR

module sub (IN, OUT);
  input IN;
  output OUT;
  assign OUT = IN;             
endmodule

?

Then I can use write_verilog to add the feature.

[jhkim-pii]

You cannot reproduce it with OpenSTA.
I recommend using the new regression only in the OpenROAD PR. The PR contains the fix in OR side, you should extract the new test case only.

OR PR:
https://github.com/The-OpenROAD-Project/OpenROAD/pull/9877/changes#diff-041ff8c687d1ba61eb0bc899635e0389657b3c189f53e8127faaa85fff988a51R854-R895

src/rsz/test/cpp/TestBufferRemoval3.cc

// Regression test for feedthrough buffer removal
//
// Design: top has a register driving child_mod's data_i (internal wire),
//   and child_mod's data_o connects to a top-level output port.
//   Inside child_mod, data_i -> BUF_X1 -> data_o (feedthrough buffer).
//
// When remove_buffers removes the feedthrough buffer, the fix in
// UnbufferMove.cc detects the feedthrough and keeps the input ModNet
// as the survivor.  This ensures VerilogWriter emits
// "assign data_o = data_i;" correctly.
TEST_F(BufRemTest3, FeedthroughAssign)
{
  std::string test_name = "TestBufferRemoval3_feedthrough";
  readVerilogAndSetup(test_name + ".v", /*init_default_sdc=*/false);

  // Verify the feedthrough buffer exists before removal
  odb::dbModule* child_mod = block_->findModule("child_mod");
  ASSERT_NE(child_mod, nullptr);
  odb::dbInst* buf_inst = block_->findInst("u_child/u_ft");
  ASSERT_NE(buf_inst, nullptr) << "Feedthrough buffer u_child/u_ft not found";

  // Before remove_buffers: two separate ModNets
  odb::dbModBTerm* bt_in = child_mod->findModBTerm("data_i");
  odb::dbModBTerm* bt_out = child_mod->findModBTerm("data_o");
  ASSERT_NE(bt_in, nullptr);
  ASSERT_NE(bt_out, nullptr);
  EXPECT_NE(bt_in->getModNet(), bt_out->getModNet())
      << "ModNets should be separate before remove_buffers";

  // Run remove_buffers — the fix in UnbufferMove.cc detects the
  // feedthrough and forces the input ModNet to survive.
  resizer_.removeBuffers({});

  // After remove_buffers: buffer is gone
  EXPECT_EQ(block_->findInst("u_child/u_ft"), nullptr)
      << "Feedthrough buffer should be removed";

  // write_verilog should emit "assign data_o = data_i;" for the
  // feedthrough since port_name("data_o") != net_name("data_i").
  writeAndCompareVerilogOutputFile(test_name, test_name + "_post.v");
}