CTS-0105: hierarchical synthesis output buffers incorrectly have dbSourceType::TIMING

[mguthaus]

Description

CTS-0105 ("Net already has clock buffer... Skipping") still fires on OpenROAD 26Q1-2966-g29d97c45b3 despite the fix in PR #7134 (commit 25acd37).

The fix correctly checks inst->getSourceType() == dbSourceType::TIMING before skipping, but all Yosys SYNTH_HIERARCHICAL output port buffers arrive in the ODB with source type TIMING instead of NETLIST. So the check passes and CTS still skips the clock net.

Root cause

When a clock input is forwarded to an output port (e.g., AXI m_aclk = clk), Yosys hierarchical synthesis inserts a buffer (output####) on the passthrough path. By the time CTS runs, these buffers have dbSourceType::TIMING in the ODB — even though no CTS or timing repair step inserted them. This causes the PR #7134 fix to incorrectly classify them as CTS-inserted buffers and skip the clock net.

Verified with OpenROAD Tcl on the post-placement ODB (before CTS runs):

output10: master=BUFx2_ASAP7_75t_R source=TIMING
output11: master=BUFx2_ASAP7_75t_R source=TIMING
...

All output* instances from Yosys have TIMING source — not just the one on the clock net.

Reproducer

Minimal 40-line design — a counter with assign clk_out = clk:

clk_passthrough.v

module counter (
    input  wire        clk,
    input  wire        reset,
    input  wire [7:0]  d,
    output reg  [7:0]  q
);
    always @(posedge clk) begin
        if (reset)
            q <= 8'b0;
        else
            q <= q + d;
    end
endmodule

module clk_passthrough_top (
    input  wire        clk,
    input  wire        reset,
    input  wire [7:0]  din,
    output wire [7:0]  dout,
    output wire        clk_out
);
    assign clk_out = clk;

    counter u_counter (
        .clk   (clk),
        .reset (reset),
        .d     (din),
        .q     (dout)
    );
endmodule

constraint.sdc

current_design clk_passthrough_top
set clk_period 500
create_clock -name clk -period $clk_period [get_ports clk]
set_input_delay  [expr $clk_period * 0.2] -clock clk [all_inputs -no_clocks]
set_output_delay [expr $clk_period * 0.2] -clock clk [all_outputs]
set_false_path -from [get_ports reset]

Build with ORFS on asap7 with SYNTH_HIERARCHICAL=1, CORE_UTILIZATION=50.

CTS log output:

[INFO CTS-0007] Net "clk" found for clock "clk".
[WARNING CTS-0105] Net "clk" already has clock buffer output10. Skipping...
[WARNING CTS-0105] Net "clk_out" already has clock buffer output10. Skipping...
[WARNING CTS-0083] No clock nets have been found.
[INFO CTS-0008] TritonCTS found 0 clock nets.
[WARNING CTS-0082] No valid clock nets in the design.

Impact

The NyuziProcessor design (352k cells, 55 SRAM macros, 41,040 clock sinks) forwards clk to output m_aclk for AXI. CTS inserts 0 buffers, leaving all flops on a raw unbuffered clock net. Post-global-route extraction yields ~388 ns of clock insertion delay on a 1.6 ns target period, making the design unroutable.

Suggested fix

The source type issue is upstream of CTS — the output* buffers from Yosys synthesis should have dbSourceType::NETLIST, not TIMING. Either:

1. Fix whatever ORFS flow step is setting TIMING source on synthesis-inserted buffers, or
2. Have CTS use a more robust heuristic than source type alone (e.g., check instance naming convention, or check if the buffer was present before any CTS/resizer pass)

Related

• cts fails to build clock tree when clock is also an output port #6352 — original CTS-0105 report
• cts: clock tree not generated when clock port is buffered in netlist with a buffer cell used by CTS #6517 — duplicate
• CTS fix wrong clock net skiping #7134 — fix (merged April 2025, present in this build but ineffective due to wrong source type)

Version

• OpenROAD: 26Q1-2966-g29d97c45b3
• ORFS image: docker.io/openroad/orfs:26Q2-32-gca75a11e2

[mguthaus]

Here is a test case.

cts_skip_repro.tar.gz

[mguthaus]

Workaround

For anyone hitting this: the root cause is that Yosys hierarchical synthesis output port buffers (output*) arrive in the ODB with dbSourceType::TIMING instead of NETLIST. This fools the PR #7134 fix into thinking they are CTS-inserted buffers.

A PRE_CTS_TCL script that resets the source type before CTS runs fixes the issue:

# pre_cts.tcl — workaround for OpenROAD #10177
set block [[[ord::get_db] getChip] getBlock]
set count 0
foreach inst [$block getInsts] {
    if {[string match "output*" [$inst getName]] &&
        [$inst getSourceType] == "TIMING"} {
        $inst setSourceType NETLIST
        incr count
    }
}
puts "PRE_CTS workaround: reset $count output buffer(s) from TIMING to NETLIST"

In ORFS config.mk:

export PRE_CTS_TCL = path/to/pre_cts.tcl

Or in bazel-orfs sources:

sources = {
    "PRE_CTS_TCL": [":pre_cts.tcl"],
},

Verified on a minimal test case (8 flops + assign clk_out = clk, SYNTH_HIERARCHICAL=1, asap7) and on the full NyuziProcessor design (352k cells, 41k clock sinks) — CTS now builds the clock tree and routing completes normally.

[maliberty]

Your analysis is off. The buffer doesn't come from yosys nor does it relate to SYNTH_HIERARCHICAL. It is created by buffer_ports in the global_place step. TIMING is a correct type for a buffer inserted for optimization (in this case to buffer the output).

The real issue is that buffer prevents CTS from happening. We can skip creating it in Resizer::bufferOutputs with

          // Leave clock nets to CTS
          && !sta_->isClock(net, sta_->cmdMode())

but then CTS doesn't put any buffer between the input and output either which isn't good.

Either we need to not buffer the output pre-CTS and CTS can buffer the output or we can put in the buffer pre-CTS but then CTS needs to handle the other fanouts.

[mguthaus]

Ok. In any case, CTS doesn't run when it should.

[mguthaus]

You're right — I verified that the buffer comes from buffer_ports in the global placement resizer (3_3_place_gp), not from Yosys hierarchical synthesis:

[INFO RSZ-0028] Inserted 9 BUFx2_ASAP7_75t_R output buffers.

The bug reproduces identically without SYNTH_HIERARCHICAL=1. TIMING is the correct source type for these buffers, so the PR #7134 source-type check can't distinguish them from CTS-inserted buffers.

Updated the issue title/description would be more accurate as: resizer buffer_ports on a clock output port prevents CTS from building the clock tree.

The workaround (resetting source type to NETLIST pre-CTS) still works in practice, but the proper fix is as you described — either skip buffering clock output ports in Resizer::bufferOutputs, or have CTS handle the remaining fanouts when a clock output buffer already exists.