I want to get a simple and_gate layout. Please help me.

[Luffy-HJ]

I already know there is a web site which describes a full flow of creating an analog layout of a chip.

But there is too much background knowledge I need to understand it.

I really want to work as an EDA Tool Developer.

I asked chatGPT about the road through which I must go. He told me to code a verilog file (In my opinion, I thought it reasonable to taste a little with simple and_gate.v) and synthesize it with Yosys. And if I touch the synthesized result with openROAD, gds file will be made so I can see the layout about it with my eyes.

But there are so many errors.

[ERROR] Floorplan initialization methods are mutually exclusive, pick one.

Warning: There are X input/output ports missing set_input/output_delay.

Warning: There is 1 unconstrained endpoint.

[WARNING IFP-0028] Core area lower left (1.000, 1.000) snapped to (1.380, 2.720).

[ERROR PDN-0185] Insufficient width (...) to add straps on layer met4 in grid "grid" ...

[ERROR GPL-0130] No rows defined in design. Use initialize_floorplan to add rows.

[WARNING RSZ-0021] no estimated parasitics. Using wire load models.

These are only a part of the iceberg. There have been so many errors until I succeed to install it and execute the example gcd layout.

I'm really exhausted. What must I do? Well, was the roadmap the chatGPT gave to me wrong? Should I choose another way to be an EDA Tool Developer?

[maliberty]

OpenROAD & yosys are for digital design, not analog. Learning to use the tools is a good start on the path. You could start with https://openroad-flow-scripts.readthedocs.io/en/latest/tutorials/FlowTutorial.html which should run successfully. Then try to examine what it does, how it works, and make small changes. In the long run you need strengths in programming (usually in c++), an understanding of chip design (your customers' needs). If you plan to work in backend tools you'll want some understand of manufacturing as well.