Detailed routing loops instead of straight wire...

[oharboe]

I've been fixing some problems in mock-array in positioning of macros and pins not being aligned and now things are working well.

However, I found this curious thing when inspecting, a detailed routing loop :-)

I don't see any reason why a horizontal wire wouldn't work here...

Any ideas or insights?

The above can be found if creating a flow/settings.mk file:

export DESIGN_CONFIG?=designs/asap7/mock-array/config.mk
export MOCK_ARRAY_DATAWIDTH?=8
export MOCK_ARRAY_TABLE?=8 8 4 4 5 5
export MOCK_ARRAY_SCALE?=80

and running make verilog and make

Various interesting things can be seen in detailed routing:

• almost all the wires are vertical/horizontal between "Element" macros. The loop above is untypical, usually it's just a slight horizontal/vertical deviation.
• there are hold cells in the middle to the right

Hold cells have to be placed outside to the right of the array, hence many non-vertical vertical wires between those two elements.

[maliberty]

@osamahammad21 any thoughts on the loop?

[oharboe]

A feature request filed: #3634