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avoid duplicate ports/signals in hier verilogs #6138

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avoid duplicate ports/signals in hier verilogs

avoid duplicate ports/signals in hier verilogs #6138

Triggered via pull request April 28, 2026 21:55
@openroad-ciopenroad-ci
synchronize #10289
The-OpenROAD-Project-staging:debug_write_verilog_bug
Status Success
Total duration 1m 0s
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github-actions-are-differences-found.yml

on: pull_request
No-Diffs-In-Ok-Files
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