flow: move repair_tie_fanout into synth_odb.tcl before remove_buffers

PR #4187 moved remove_buffers, replace_arith_modules and
repair_timing_helper out of floorplan.tcl into synth_odb.tcl, but left
repair_tie_fanout behind in floorplan.tcl. That flipped the relative
order: in master repair_tie_fanout had run *before* remove_buffers (a
load-bearing invariant the dropped ordering comment was guarding); in
the new flow it ran against the already-unbuffered netlist.

The behavior difference is small but real. On asap7/ibex it produced
14 TIELOx1 instances instead of 15, propagated through global
placement, and the design entered CTS in a state that converged to
~5x worse setup TNS:

    cts setup TNS  master -961 ps   PR (pre-fix) -5584 ps

Move repair_tie_fanout into synth_odb.tcl ahead of replace_arith_modules
and the remove_buffers / repair_timing_helper branch so the original
ordering is preserved. Re-running asap7/ibex with this fix gets the
TIELO count back to 15. TIE_SEPARATION and SKIP_REPAIR_TIE_FANOUT now
live in the synth stage in variables.yaml/json so they survive the
synth-stage erase_non_stage_variables call.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>

Author: oharboe

flow/scripts/floorplan.tcl

@@ -75,22 +75,6 @@ if { [env_var_exists_and_non_empty FASTROUTE_TCL] } {
 
 source_env_var_if_exists FOOTPRINT_TCL
 
-if { !$::env(SKIP_REPAIR_TIE_FANOUT) } {
-  # Repair tie lo fanout
-  puts "Repair tie lo fanout..."
-  set tielo_cell_name [lindex $::env(TIELO_CELL_AND_PORT) 0]
-  set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]]
-  set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $::env(TIELO_CELL_AND_PORT) 1]
-  repair_tie_fanout -separation $::env(TIE_SEPARATION) $tielo_pin
-
-  # Repair tie hi fanout
-  puts "Repair tie hi fanout..."
-  set tiehi_cell_name [lindex $::env(TIEHI_CELL_AND_PORT) 0]
-  set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
-  set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $::env(TIEHI_CELL_AND_PORT) 1]
-  repair_tie_fanout -separation $::env(TIE_SEPARATION) $tiehi_pin
-}
-
 puts "Default units for flow"
 report_units
 report_units_metric

flow/scripts/synth_odb.tcl

@@ -51,6 +51,27 @@ check_setup
 set num_instances [llength [get_cells -hier *]]
 puts "number instances in verilog is $num_instances"
 
+# repair_tie_fanout must run before remove_buffers and the timing-driven
+# transforms below: a single tie that drives multiple buffers (each driving
+# multiple loads) needs the fanout split per-buffer-load before remove_buffers
+# collapses the buffers, otherwise the resulting tie fanout is a different
+# netlist and cascades into worse setup TNS at CTS (~5x on asap7/ibex).
+if { !$::env(SKIP_REPAIR_TIE_FANOUT) } {
+  # Repair tie lo fanout
+  puts "Repair tie lo fanout..."
+  set tielo_cell_name [lindex $::env(TIELO_CELL_AND_PORT) 0]
+  set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]]
+  set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $::env(TIELO_CELL_AND_PORT) 1]
+  repair_tie_fanout -separation $::env(TIE_SEPARATION) $tielo_pin
+
+  # Repair tie hi fanout
+  puts "Repair tie hi fanout..."
+  set tiehi_cell_name [lindex $::env(TIEHI_CELL_AND_PORT) 0]
+  set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
+  set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $::env(TIEHI_CELL_AND_PORT) 1]
+  repair_tie_fanout -separation $::env(TIE_SEPARATION) $tiehi_pin
+}
+
 if { [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } {
   # Enable sanity checker until replace_arith_modules becomes stable
   set_debug_level ODB replace_design_check_sanity 1

flow/scripts/variables.json

@@ -365,7 +365,7 @@ TIE_SEPARATION:
   description: |
     Distance separating tie high/low instances from the load.
   stages:
-    - floorplan
+    - synth
   default: 0
 UNSET_ABC9_BOX_CELLS:
   description: |
@@ -810,9 +810,9 @@ SKIP_CTS_REPAIR_TIMING:
   default: 0
 SKIP_REPAIR_TIE_FANOUT:
   description: >
-    Skip repair_tie_fanout at floorplan step.
+    Skip repair_tie_fanout at synth step.
   stages:
-    - floorplan
+    - synth
   default: 0
 MIN_ROUTING_LAYER:
   description: |