sim_cache.sh

#!/bin/bash
MODELSIM_BIN="/home/neil/intelFPGA/20.1/modelsim_ase/bin"

rm -rf rtl_work

"$MODELSIM_BIN"/vlib rtl_work
"$MODELSIM_BIN"/vmap work rtl_work

# --- COMPILE ALL YOUR DESIGN UNITS (HDL) FIRST ---
"$MODELSIM_BIN"/vlog -sv -work work hdl/ff_array.sv
"$MODELSIM_BIN"/vlog -sv -work work hdl/cache.sv
# --- THIS IS THE MISSING LINE ---
"$MODELSIM_BIN"/vlog -sv -work work hdl/axi_cache_adapter.sv

# --- NOW COMPILE YOUR TESTBENCH & VERIFICATION (HVL) ---
"$MODELSIM_BIN"/vlog -sv -work work hvl/memory.sv
"$MODELSIM_BIN"/vlog -sv -work work hvl/testbench.sv

# --- RUN SIMULATION ---
"$MODELSIM_BIN"/vsim -t 1ps -L rtl_work -L work testbench \
-voptargs="+acc" \
+input_path=$1 \
-do "
  transcript off;
  view structure;
  view signals;
  add wave -r -h *;
#   configure wave -delta on;
  run -all;
#   quit -f;
"