Contra SNES (MSU): inaccurate one frame rows of pixels in menus

[littlegamer87]

Raising a separate issue for this, last mention got buried in #423 but it seems to be the only ppu bug that is still open.

MSU version can be retrieved from the archive as "Contra SNES" under infidelity account. Launch game and push right in the game selection menu with the posters and notice the rows of pixels for one frame at the bottom half of the screen halfway through the scroll animation.

Real hw recording from @paulb-nl : https://github.com/user-attachments/assets/e76ddea4-e2fa-4c7b-816c-0bbb139a77fd

On the core, scrolling between option 1 (NES) to 2 (Arcade) to 3 (Movie OST) shows (rows of) pixels that do not seem to appear on real hardware, but I also notice I can't reproduce every attempt. Might depend on input timing and take a few tries. Scrolling further from option 3 back to 1 shows one or two white rows of pixels - only this transition seems to match real hw.

[paulb-nl]

I think it is related to the VRAM access/rendering being slightly delayed (half or whole cycle) on original hardware compared to the core. On the Transistor simulation we can see that VRAM addresses vaa and vab are delayed/latched from the internal addresses _int_vaa and _int_vab.

I posted a test rom here with the Contra graphics #423 (comment)

It shows the same glitches on hardware and the core but on original hardware the glitch starts out invisible and on the core it starts out flickering.

If I change the Vertical IRQ to the last line then this is how it starts on original hardware without changing the Horizontal IRQ. Setting the IRQ one cycle later by pressing the R button one time will show a stable blue/green tile.

Also with the Force Blank fetching test from here #430 I have to press R two times on original hardware to make the red N show up but on the core I only need to press R one time.

Start of the Force Blank test on original hardware. The green pixels start before the G letter below it.

[paulb-nl]

Another difference is that with original hardware PPU writes happen while PAWR_n is low but the core also needs SYSCLK_CE to be high so PPU writes on the core are effective a bit later compared to hardware.